As is well known, a Double Data Rate (DDR), which can input and output data in synchronization with both rising edge and falling edge of a clock upon input and output of the data, operates in a burst mode in order to effectively perform continuous read or write operations.
The burst mode is set by a first burst signal BL4 and a second burst signal BL8. When the first burst signal BL4 is set to a high level, a burst length is set to 4 and thus data of 4 bits is continuously inputted or outputted by a single command. When the second burst signal BL8 is set to a high level, the burst length is set to 8 and thus data of 8 bits is continuously inputted or outputted by a single command. In general, since the burst length is defined up to 8 in a DDR2, it is easy to realize an internal command generation circuit for providing the burst mode.
Meanwhile, there has been developed a Low Power DDR2 (LPDDR2) which can markedly improve power consumption and data transfer speed of mobile devices. The DDR2 can realize a data transfer speed of 800 Mbps, which is the highest speed in the field, at a voltage of 1.2 V, and is applied with ultra-fine process of 66 nm technology to thereby allow a mobile memory chip to be packaged to a size of 9 mm*12 mm. Since the burst length is defined up to 16 in the LPDDR2, there has been a problem that realization of a burst mode control circuit for generating a column access signal which controls a burst mode operation is quite complex. Such problem will be described with reference to FIG. 1, which shows a conventional burst mode control circuit used in LPDDR2.
A conventional burst mode control circuit shown in FIG. 1 is used when a 4-bit prefetch is applied, and includes an internal command generation unit 10, a burst pulse control unit 12 and a column access signal generation unit 14.
The internal command generation unit 10 decodes a plurality of external commands CMD<0:3> in response to a clock signal CLK to generate a read command RD_CMDP, a write command WT_CMDP and an interrupt end signal BST. The read command RD_CMDP is a pulse signal generated upon a read operation, the write command WT_CMDP is a pulse signal generated upon a write operation and the interrupt end signal BST is a level signal generated from a pulse signal to pause the burst mode by an interrupt.
The burst pulse control unit 12 controls a pulse number of a burst pulse YBURSYP according to a first burst signal BL4 and a second burst signal BL8 when a pulse of the read command RD_CMDP is inputted upon the read operation or a pulse of the write command WT_CMDP is inputted upon the write operation. More specifically, the pulse of the burst pulse YBURSTP is not generated when the burst length is set to 4 and only the first burst signal BL4 is thus at a high level, the burst pulse YBURSTP is generated in one pulse when the burst length is set to 8 and only the second burst signal BL8 is thus at a high level, and the burst pulse YBURSTP is generated in three pulses when the burst length is set to 16 and both the first burst signal BL4 and the second burst signal BL8 are at a low level.
The column access signal generation signal 14 generates a column access signal INT_CASP from the burst pulse YBURSTP in synchronization with the clock signal CLK. Like the burst pulse YBURSTP, the column access signal INT_CASP is not generated as a pulse when the burst length is set to 4, is generated in one pulse when the burst length is 8, and is generated in three pulses when the burst length is 16. The burst mode is carried out when the column access signal INT_CASP is generated as such and this is because 4-bit data is basically inputted or outputted in the case that the 4-bit prefetch is applied and 4-bit data is inputted or outputted each time a pulse of the column access signal INT_CASP is generated.
Since the burst pulse control unit 12 included in the conventional burst mode control circuit configured as described above includes three clock shifters in order to provide a burst mode in which the burst length is set to 16, there has been a problem that realization of the circuit is quite complex and current consumption is very large.